<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" version="2.0">
  <channel>
    <title>blog</title>
    <link>https://blog.morphing.in/blog</link>
    <description />
    <language>en</language>
    <pubDate>Thu, 04 Jul 2024 11:38:33 GMT</pubDate>
    <dc:date>2024-07-04T11:38:33Z</dc:date>
    <dc:language>en</dc:language>
    <item>
      <title>Using An Application Specific Instruction Set Processor To Parallelize Monte Carlo Heston Algorithms For Getting Better Performance On FPGA Based Systems</title>
      <link>https://blog.morphing.in/blog/using-an-application-specific-instruction-set-processor-to-parallelize-monte-carlo-heston-algorithms-for-getting-better-performance-on-fpga-based-systems</link>
      <description>&lt;img src="https://blog.morphing.in/hubfs/Generated%20Blog%20Post%20Images/A%20complex%20digital%20circuit%20board%20with%20multiple%20interconnected%20components%2c%20including%20FPGA%20chips%20and%20specialized%20processors%20designed%20for%20running%20Monte%20Carlo%20Heston%20algorithms..jpeg" alt="A complex digital circuit board with multiple interconnected components, including FPGA chips and specialized processors designed for running Monte Carlo Heston algorithms."&gt;
&lt;p&gt;Unleash the full potential of FPGA-based systems by leveraging application-specific instruction set processors for the parallelization of Monte Carlo Heston algorithms.&lt;/p&gt;</description>
      <content:encoded>&lt;img src="https://blog.morphing.in/hubfs/Generated%20Blog%20Post%20Images/A%20complex%20digital%20circuit%20board%20with%20multiple%20interconnected%20components%2c%20including%20FPGA%20chips%20and%20specialized%20processors%20designed%20for%20running%20Monte%20Carlo%20Heston%20algorithms..jpeg" alt="A complex digital circuit board with multiple interconnected components, including FPGA chips and specialized processors designed for running Monte Carlo Heston algorithms."&gt;
&lt;p&gt;Unleash the full potential of FPGA-based systems by leveraging application-specific instruction set processors for the parallelization of Monte Carlo Heston algorithms.&lt;/p&gt;  
&lt;img src="https://track-na2.hubspot.com/__ptq.gif?a=46371591&amp;amp;k=14&amp;amp;r=https%3A%2F%2Fblog.morphing.in%2Fblog%2Fusing-an-application-specific-instruction-set-processor-to-parallelize-monte-carlo-heston-algorithms-for-getting-better-performance-on-fpga-based-systems&amp;amp;bu=https%253A%252F%252Fblog.morphing.in%252Fblog&amp;amp;bvt=rss" alt="" width="1" height="1" style="min-height:1px!important;width:1px!important;border-width:0!important;margin-top:0!important;margin-bottom:0!important;margin-right:0!important;margin-left:0!important;padding-top:0!important;padding-bottom:0!important;padding-right:0!important;padding-left:0!important; "&gt;</content:encoded>
      <category>Quantitative Finance</category>
      <category>Monte Carlo Algorithms</category>
      <category>Computational Finance</category>
      <pubDate>Thu, 04 Jul 2024 11:27:33 GMT</pubDate>
      <author>deepak@morphing.in (Deepak Shapeti)</author>
      <guid>https://blog.morphing.in/blog/using-an-application-specific-instruction-set-processor-to-parallelize-monte-carlo-heston-algorithms-for-getting-better-performance-on-fpga-based-systems</guid>
      <dc:date>2024-07-04T11:27:33Z</dc:date>
    </item>
  </channel>
</rss>
